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Altera_Forum
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15 years ago

Cascading gated clock bufs in Arria 2 GX

I need (at least) two levels of gated clocks in a particular design. For example: Input pin drives signal called CLKIN. The CLKIN drives global or regional clock net called CLK1A and CLK1B ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Possible solution 1: Replace your clock gating with clock enables.

If you can't rewrite all the code to insert clock enables, Quartus has an option to convert clock gating into clock enables. You may have to rewrite the clock gating code to match Altera's template for this.

Possible solution 2:

Replace your two levels of gating with a single level. Combine EN1A and EN2A to produce the gated clock CLK2A. Same for CLK2B.

In this case, I assume you are using ALTCLKCTRL to gate the clocks. It's the only way to have low skew clock gating/muxing on Altera's FPGAs.