Carry chain on Cyclone V GX using a 1bit adder

Hi,
example of full adder implemented with lcell_comb wysigwyg primitive can be found in Advanced Synthesis Cookbook, the module is part of basic_adder.v It can be directly used for Cyclone V because Stratix utilizes same 6-input LUT logig cell.

Problem is that cin and cout can't be directly routed to I/O pins, carry chain can only start and end in other logic cells, as gate level logic circuit of full adder shows. When designing with cyclonev_lcell_comb, the interconnect lcells are generated automatically.

Regards
Frank