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benji1312
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1 year ago

Carry chain on Cyclone V GX using a 1bit adder

Hello everyone, I am new to the world of FPGAs, and I need to do a Time to Digital Converter, thus I would need to use a carry chain to precisely mesure time. I tried a few different things: - Usi...
Fpga Devkit
benji1312's avatar
benji1312
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1 year ago

Hello,

So here is my RTL view with the 4bit LPM_ADD_SUB,

And here is the chip planner view :

For the RTL view, it looks the same as the 1bit version (with 4 bit instead of 1 obviously), and on the chip planner we can clearly see that the carry chain is used, even though some optimization seems to occur as we only use 3 ALM.

Thank you,

Best regards,

Benjamin