carry chain delay difference between real test and Timequest analysis result

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I have heard about TDC on FPGAs but I have doubts about its precision as it should take into account clock tree delays, timing violations, fitting variation, optimisation and needs some sort of averaging

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Thanks for your reply.

Well, as you look into FPGA based TDC implementation, you will see that these problems you said all will be handled commendably.

Here my problem is not how to implement TDC in FPGA, my problem is why TimeQuest analysis result is different from real test.

Since TimeQuest plays a critical role in regular FPGA designs, i need to figure out what is wrong? is my test result wrong? or something else.

I have used the same method to acquire the carry delay of Cyclone-IV, the real test result is well fitted into Timequest analysis result, while for Cyclone-V, this is not the case.

I think the problem could be replicated easily, i need a confirmation from someone else.

Best Regards,

ingdxdy