carry chain delay difference between real test and Timequest analysis result

Thanks much for your reply, Jerry, and sorry for my delayed response.

As you said, there are two dedicated adders in a ALM, and according to TQ result, the second adder delay is 0ps, while the first adder contributes the main component of TDL.

the granularity of delay element is not as uniform as in CIV, but this is not problem. i have seen other peoples works where they implement TDCs in 28nm(or 20nm?) Xilinx FPGAs, the delay elements there are either non-uniform and there exist many zero-wide bins.

Generally, TDCs implemented in more advanced process FPGAs (28nm and below) need bin realignment, for IC delays including clock skews play a more important role than before to decide bins positions. the tuition of bins are arranged according to their physical locations should be adjusted.

However, the purpose of my posting this thread is not to discuss how to implement TDCs in CycloneV, but the real test delay value is different from TQ result which makes me puzzled.

B&W,

ingdxdy