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Well, i chained 420 ALMs vertically, a carry signal is generated by an input (active high). then the carry signal is propagated along the (adder) chain.
A 250MHz system clock is used to sample the carry signal position, then i could get to know how many ALMs the carry signal is passed within a 250MHz period(positions at two adjacent clock edges can be obtained and then subtracted).
according to test result, the carry signal propagates about 360 ALMs in a 250MHz period, so i get average carry delay per ALM is 4000ps/360=11ps.
you could look at the basic idea of FPGA based TDC implementation to get a deep understanding.
Best Regards,
ingdxdy
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I have heard about TDC on FPGAs but I have doubts about its precision as it should take into account clock tree delays, timing violations, fitting variation, optimisation and needs some sort of averaging
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