Capture timing at SERDES

You report is very unclear. A 500 MHz ADC or DAC won't use serialized data pathes rather than parallel LVDS connections. In so far I don't understand how SERDES comes into play.

In case of SERDES, you need to distinguish between bit phase alignment (sampling window adjustment) and word alignment. Stratix III hardware SERDES have powerful means for both purposes. But if the LVDS inputs are bypassing the SERDES block, no phase alignment is provided.

The usual method to achieve correct sampling of fast data streams is to connect the output clock of the ADC to the FPGA.