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Altera_Forum's avatar
Altera_Forum
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8 years ago

can't see enough FMAX

hello I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ). it has 80 pairs of LVDS inputs as DDRIO input. when I compile the project, it says FMAX is 103MHz that is too slower than...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

hello sstrell.

thanks for your answer.

actually, I do not know SDC file well.

I just wrote those.

for 300 MHz clock is this.

create_clock -name {lvdsclk300} -period 3.333 -waveform { 0.000 1.666 } [get_ports {cam_clk[3]}]

and also for delay, I wrote this statement for pins cam_data[0] to cam_data[79]

set_input_delay -add_delay -clock [get_clocks {lvdsclk300}] 0.000 [get_ports {cam_data[0]}]