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Altera_Forum
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7 years ago

can't see enough FMAX

hello I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ). it has 80 pairs of LVDS inputs as DDRIO input. when I compile the project, it says FMAX is 103MHz that is too slower than...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

What do your SDC timing constraints look like? How is your clocking set up in your design. More details needed here.