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Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Can't generate program files

I'm trying to compile the hard ip ethernet 10G example design . "F-Tile Ethernet Intel® FPGA Hard IP" example design for 10GBE standalone but cant generate sof file. i get all the time this messag...
Configuration
Programmable Logic Device
  • ZiYing_Intel's avatar
    ZiYing_Intel
    2 years ago

    Hi Avichay,


    Please do ensure the OPN number in the Quartus is same as the board that you use.


    Best regards,

    zying


ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Avichay,


Please do ensure the OPN number in the Quartus is same as the board that you use.


Best regards,

zying


Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
2 years ago

Thanks for your reply.

I am trying to check the example design on my board with my QSF file.

I'm using AGFB027R24C2E2V FPGA.

This part is i the project and in the qsys setting part from where i generated the example design.

should i generate the example design with the ANLT (Auto negation and training disabled ? )

my purpose is to check the xcvr and ethernet using loop back on the Intel toolkit system console .

I should have all the licenses.

Thanks,