Can't fit fan-out of node into a single clock region

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Hi,

I've encounterred with this promblem.I use the ep2c20f256c8 ,design with 1 pll and 20 channels of lvds transmitter. input clock freq is 50MHz,pll output clocks' f is 200MHz,100MHz,50MHz,and it works well. but when i change the pll into: 200MHz,100MHz,25MHz, quartus give me an error "Can't fit <clk2> fan-out of node into a single clock region",where clk2 is the 25MHz output of pll

This is my 1st time seeing this error,What should i do?

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My problem was solved when I replaced two cascaded PLLs with a single PLL (in cyclone II).