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Altera_Forum's avatar
Altera_Forum
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9 years ago

Can't close timing on one clock domain

Hi, I've been struggling to close timing on one clock domain in my design, happens to be the one with all my control logic/ nios on it so is kind of important for getting into functional test....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That comment to add pipeline stages was a 1 click fix to my problems, it pushed my fMax up to 216MHz with no other changes! Increased the system-wide max no. of pipeline stages from 1 to 4.

If only I knew about it before (it does hide slightly in the Qsys GUI tbh).

Very content with this fix as the overall latency is not important for my application.

Thanks very much!