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Altera_Forum's avatar
Altera_Forum
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9 years ago

Can't close timing on one clock domain

Hi, I've been struggling to close timing on one clock domain in my design, happens to be the one with all my control logic/ nios on it so is kind of important for getting into functional test....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks for the reply,

I'm actually running on Arria V GZ, so either Nios II flavour should be fine at 200MHz.

It makes me wonder however, if only part of the logic on the domain was unrouteable for 200MHz, would the I see such massive failure as per the histogram, or would all the logic P&R correctly except the incompatible stuff?

For example if I had a fully constrained placement at 200MHz, and I added a small IP component only good for 150MHz, what would the histogram look like?