Honored ContributorFirsr I built a project includes Nios II ,memories ,it works.
When I added a DDR2 SDRAM controller, not only the DDR2 does't work but also the system . The pin assignment has been finished. Who can tell me why? Thank you!
Honored Contributorwhich types of errors that you are getting?
and what is your program memory,reset and exception memories?Honored ContributorNo error,but the system cannot work.
program memory,reset and exception memoriesare onchip memory.Honored ContributorHonored ContributorDoes the nios2-download tells you that the processor can not be paused? --> check the reset signals for DDR2 controller (High Performance DDR2 Controller with Altmemphy has a reset_n signal as a top level port for the SOPC Builder System).
Does the nios2-download tells you Verify Failed? --> If you are downloading to DDR2 there may be problems with signal integrity. Try to build a memtest to run from internal memory. I assume that by "download" you mean that you are trying to download a program. I would not give to much confidence to simulation when a designed based on Altemphy or uniphy are included in the project because these two *phy do not support post fitting simulation (found in the user guides).Honored ContributorHonored ContributorYou do not use it, fine. I am quite sure that with the altmemphy based DDR2 controller, a reset_n signal appears in the SOPC Builder. It may appear even with the uniphy based controller (never used it). Are you sure this reset is correctly connected? If left floating or grounded it may give a reset to the controller, I am not sure that the controller while in reset do not asks for a system reset.
Honored ContributorHonored ContributorThat reset signal affects also the physical behaviour.
Honored ContributorHonored ContributorIt depends on your design. If you have a reset button and it has the correct polarity, try connecting it. Or you can connect it to a bit of a PIO if you want the system to self reset.
If these signals are active high while the reset_n is active low, put a NOT gate. I think that someone else, just yesterday, had a similar problem and went around it stucking the reset_n to high level (a signal fixed to '1' or a VCC primitive in bdf file)
