Cannot connect PLL to internal signal in Cyclone IV

Hi FvM, thank you for the reply. Yes, my synthesizer uses logic generated clocks. So I understand that it is not possible to route the output of my synthesizer to a PLL input. I am trying to port a design from Xilinx FPGAs to Altera/Intel, and Cyclone IV was my first try. All Xilinx FPGAs that I've tried so far (Spartan 3, 3A, 3E, 6, and Zynq) allow me to connect the logic generated synthesizer output clock to a PLL so I am surprised to learn that Cyclone IV does not allow this connection.