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Honored Contributor
Honored ContributorCannot connect PLL to internal signal in Cyclone IV
Hello Everyone, I am trying to place a PLL macro after a frequency synthesizer in a Cyclone IV FPGA and it looks like this is not possible. As a workaround I had to route the synthesizer output t...
Altera_ForumHonored Contributor
Honored ContributorWhat is the "frequency synthesizer"? A programmable divider implemented in LEs? That's in fact not supported. Cascading PLLs is basically possible, but logic generated clocks as PLL input isn't.
