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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Cannot access the JTAG port of Arria10 SoC

There’re two Arria 10 SoCs in my design, the follwoing picture indicates the JTAG chain on board. Chip A and Chip B share the same TCK & TMS. TCK is pulled down to GND and TMS is pulled up to VCCP...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, You can confirm by measuring the nConfig and nStatus pin where both should be high. If you are referring to USB-Blaster user guide, the TDI is referring to the device TDI.
SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thank you. Here's my update.

The waveforms of both devices' nSTATUS pins are rectangular waves, and one's frequency is 516Hz while the other one is 542Hz.

I refer to relevant hanbook, after sampling MSEL, nSTATUS is released high and then pulled low if configuration error occurs.

In my design, I define MSEL=011 with pull-up resistor to VCCPGM and pull-down reststor to GND, which indicates AS×4 mode. Each of the devices has an attached EPCQL1024.

Is it possible that the devices try to load configuration data from EPCQL1024 after power-up then fail, so the waveform of nSTATUS is rectangular wave, resulting the reset of the device and JTAG periodically?

If the answer is yes, how can I solve this problem to relase the device from reset state?

Thanks, regards.