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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can we use a differential clock input as 2 single-ended clock inputs?

I use a FPGA of the Stratix GX II family, EP2SGX90FF1508.

In my design I have 3 differential input clocks on an external connector but I actually need 5 single ended clock inputs.

Is it possible to use a differential input as 2 single-ended inputs?

Do we need to configure something on Quartus for that?

Thanks for you help!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Is it possible to use a differential input as 2 single-ended inputs?

    --- Quote End ---

    Yes.

    --- Quote Start ---

    Do we need to configure something on Quartus for that?

    --- Quote End ---

    Assign a single ended I/O standard and the respective pin location for the clock signals.