Can unused VREFB pins be FLOATED in Cyclone10 LP ?

Hello , Thank you for the question , To answer your question why , Can you kindly look at the diagram Figure 65 or 66 ? Those IO standards are voltage reference IO std.Keeping the VREF pin as floating what is the output of the buffer logic which is undefined right ? Assume now you connected to valid logic 1 or 0 , then based on the input it is predictable answer. That mean, you no need to care about what voltage you think it should be high /low since it is unused for your logic , but atleast that pin should be valid logic as HW should work as expected. Suppose in your design if you left open the VREF pin , you can configure as IO and enable the weak pull up. Hope helps . Thank you, Regards, Sree