Can the MAX10 VCCIO supply be set at 2.7V?

Addressing these in reverser order:-

2) Yes - different I/O banks can be powered at different voltages.

1a) Yes. You can power one (or more) bank(s) at 2.7V.

1b) The impact on 'performance'. This depends on what you compare it to. Altera (and Quartus) characterise I/O performance at the discrete voltages specified in the datasheet. Quartus will ask you to specify what I/O standard your pin is operating at. You'll end up having to chose a 2.5V or 3.0V I/O standard. So, Quartus will qualify your signal based on the I/O standard you chose and an assumption that you're powering the bank accordingly. So, when you power the bank at a different voltage the above assumptions are invalid.

Does this matter? This depends on what you're trying to do and will largely depend on what speed you're expecting to run the interface at.

Before powering a bank at 2.7V, you should also consider powering it at 2.5V or 3.0V anyway. Check the minimum voltage each end of the interface will generate for a logic 'high' and qualify the link for yourself. Driving 2.7V into a bank powered at 2.5V will cause you no issue, but will the other end always see a 2.5V level as a logic high? Power the bank at 3.0V and decide whether your 2.7V device will always meet the minimum FPGA threshold for a logic high. Perhaps your other device will happily tolerate receiving a 3.0V from the FPGA. If not, depending on the frequency of you signal, you could condition it externally - with a buffer or simple pot-down resistor network.

Cheers,

Alex

Alex, thanks for your rapid reply - really helpful and insightful.

My design uses a level shifter between the MAX10 (single supply at 3V3) and a flash IC running at 2V7. The flash interface is 50MHz (max) 8-bit asynchronous. The get the data to a PC I use an FTDI device from the MAX10. My goal is to make the design as small as possible, and the level shifter is one of the biggest components and hence I want to remove it.

Do you think 50MHz would be fine with a bank voltage of 2V7?

To save space, I am trying not to generate a new voltage - so I could consider powering the bank at 3.0V. I'd have to make sure the logic high qualifies for the fpga and that 3V isn't going to damage the flash device powered at 2.7V or the microcontroller (they share the same bus to the flash).

Thanks again for your insight,

James

Yes, an interface operating at 50MHz should be fine at 2.7V. I don't think you'll see any problems. Single ended 2.5V I/O will quite happily go to that speed. So, the extra 200mV will only help.

Given the asynchronous interface, I'd suggest you could simply slow the interface down if you run into problems. However, like I've said, I don't think you will.

Removing clutter - regulators & level shifters - will make for a far more elegant design. I think you're heading in the right direction.

Cheers,

Alex

Hi Alex,

I have also spoken with Altera. They did not recommend doing this. The engineer expressed concerns with the bus-hold trip-point technology in the MAX10. I can't really take the risk.

I have since calculated the 2.7V flash device with a 3.0V MAX 10 bank voltage are compatible. I already have a dedicated regulator for the MAX 10 so I will change it from 3.3V to 3.0V. I have other devices connected to the MAX 10 running interfaces at 3.3V, so I will adjust the bank voltages accordingly.

Thanks again for your input.