Can Stratix V IO pin configure with HSTL12 class 1 work at 0.8V

Hi FvM,

Many thanks for responding, your statement on PVT (Process, Voltage, Temperature) range does make sense. when i am testing and it is passing, i am only testing in a sub range of the full PVT range.

But, I am of the impression that HSTL-12 Class I is a type of digital logic signaling standard and only specifies how signals at the IO pins should be driven, terminated, and received to ensure reliable high-speed data transmission. It is not a specific circuit design. So, in the case of output buffer of the bank, am I correct to say that HSTL-12 Class I spec is just spelling out the voltage swing condition of the data that is transmitted to the downstream DUT/device. As long as the downstream DUT/device is also HSTL-12 class-I compliance, its Vil/Vih will be able to interpret a logic 0 and logic 1.

Having said that, does it also means that when i source VCCIO rail with 0.8V, the FPGA output buffer will swing between 0V to 0.8V and as long as the downstream DUT/device Vil/Vih is capable of interpretating a logic 0 and logic 1 with a acceptable margin, the operating condition is still predictable.