Can sdram be accessed by multiple processors in Cyclone II FPGA?

This is really one of the nice features of SOPC builder: you just add your second, third...etc processor in SOPC builder and make sure it is connected properly (instruction or data or both depending on your software config) to the sdram controller already in place for your first processor. SOPC Bus fabric makes all the complicated arbitration and routing for you. Your challenge will be in software, to avoid conflicts in use of the data by sectioning the ram space, or use overlapping sections as mailboxes. So: One SDRAM controller only.