can quartus break the compilation?

You say you have multiple clocks?

Are these all generated via PLLs, or do you create some of them via logic? Is data passed between the domains safely (double buffering or FIFOs)?

Is the design fully synchronous, or are you adding logic delays deliberatly to re-balance timings manually?

Are you adding a phase shift to clocks going off chip to try and align the data with the clocks without using a PLL feedback input to automatically adjust for skew?

Any of these can cause the problems you describe, and can cause situations where on some compilations it works and some it doesnt.