Can I use a clock output of a receiver as an input of a PLL?

I'm trying to implemented a transmitter and receiver on stratix II GX. On the receiver side I need a 14/15 clock, so I used the CDR output clock of the receiver as the input clock of the 14/15 PLL. I got an error which told me that the PLL must be be driven by input pin, another PLL or optionally through a clock control block. At first I thought that the CDR output clock of a receiver must be an output of a PLL. Secondly I tried to constrain the output clock of the receiver to be a global clock, but I still got the same error. Is there any solution for this case? thanks.