Hi,all. I am going to build the stand-alone NiosII system. Already, I could build PC-connecting NiosII system but I don't know how to build the stand-alone (so PC-NOT-connecting) NiosII system. What I programmed system is volatile. So I think that it is a correct answer to program the system data into a flashmemorydevice. But the system has NO flashmemorydevice.(in Qsys system,Flash Memory Interface) Can I make stand-alone NiosII system? Though I think I only add Flash Memory Interface, I don't know how to connect it to the other component. Please tell me. Thanks all.

Hi,thanks your res. Hm... When performing NiosII, must a USB cable always be connected? And, every time I put the power supply into the board, do I have to let QuartusII-Programmer to program the board?

Configuration is volatile and FPGAs lose it whenever you turn power off. If you don't want to load configuration every time with USB programmer (and usually you can't do it when the system has been deployed on the field) you need a non-volatile memory connected to fpga. This can be a serial or parallel flash memory. The common solution is using epcs serial flash devices supplied by Altera itself.

Look the "Configuration and Remote System Upgrades" chapter in the FPGA handbook.

hi yes you can make stand alone nios2 system........but you need do add a flash memory or a epcs in your system. you need set the reset vector and exception vector at sopc to cpu starts in your flash memmory.. good luck Franz Wagner

Hi, thanks all. I'll try to read "Configuration and Remote System Upgrades" chapter in the FPGA handbook. I try to program with DE2-115 board. flash memory are on the board, so I'll try it.

Can I make stand-alone NiosII system? | Altera Community

15 Replies

Altera_Forum
Honored Contributor
14 years ago
There should be a button when you perform the flash programming to tell the tools to ignore the system ID check. The System ID component is a simple little component meant to save you headaches when you accidentally have a mismatch between your .sof and intended hardware target (it's an oops detector). I highly recommend connecting it to your Nios II data master while you are the development stage of your project, once you get closer to finalizing you can remove it. It doesn't hurt to leave it in your system since it's a very small core (probably adds no more than 96 LEs to your hardware).
Altera_Forum
Honored Contributor
14 years ago
There is some online training (free) on the Altera website on configuring FPGAs that covers the various methods and options for loading configuration and state info, including host based and serial configuration devices.
Good luck
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

This is what I mean about baking the software right into the .sof file:

1) Generate your system in SOPC Builder/Qsys, make sure a large on-chip memory is present and it is configured to be pre-initialized.
2) Create and compile your software, ensure that a .hex file is created for the on-chip memory
3) Compile your hardware design in Quartus

--- Quote End ---

How do I do step# 2? I can't find a setting in the Nios tool to do this. Once I have this, do I then use this .hex file in QSYS on-chip memory configuration in place of the default "onchip_mem.hex"?
Altera_Forum
Honored Contributor
14 years ago
I figured out how to do step# 2. Actually, there are directions for this in the "Nios II Software Developer's Handbook" (May 2011), pg 2-31, "Creating Memory Initialization Files". My Nios app. will now run following power-up/reset, booting from flash.
Altera_Forum
Honored Contributor
14 years ago
I am sorry that I did not reply sooner to you.
Since other work was busy, I was not able to spare time for programming.
Since QuartusII stops because of another error now, I try your advice, after solving it.

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Can I make stand-alone NiosII system?

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