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Altera_Forum
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7 years ago

Can I expect PLL outputs to be in phase?

If I implement an ALTPLL in a cyclon V with an input clock of 26 MHz and 2 output clocks (one at 26 MHz and one at 4x 26 MHz = 104 MHz). Can I expect the two output clocks to be in phase? If...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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The output clocks are in phase and synchronous. You don't need the set_clock_groups exception unless you specifically do not want timing analysis performed on transfers between the two clock domains.

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Thanks for the quick reply. Is this the case for any PLL mode (direct, normal, etc.) or just for a certain mode?