Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan I expect PLL outputs to be in phase?
If I implement an ALTPLL in a cyclon V with an input clock of 26 MHz and 2 output clocks (one at 26 MHz and one at 4x 26 MHz = 104 MHz). Can I expect the two output clocks to be in phase? If...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The output clocks are in phase and synchronous. You don't need the set_clock_groups exception unless you specifically do not want timing analysis performed on transfers between the two clock domains. --- Quote End --- Thanks for the quick reply. Is this the case for any PLL mode (direct, normal, etc.) or just for a certain mode?
