Can HPS arm and FPGA fabric shared DDR?

Hi Jingyang,

Many thanks for your reply. The FPGA we use Agilex 7 FPGA.

"HPS Arm is able to access the DDR through the DDR Controller or HPS EMIF depending on device through the L2 Cache. The FPGA Fabirc is able to access the DDR through the FPGA2HPS bridge through the L3 cache."

the following questions:

1. If ARM put the OS region such as boot code and OS running region to offset 0x000-0x100 for example. How to ensure the FPGA fabric cannot touch that area?

2. is there any example project I can reference for the HPS connection. (ARM+FPGA access same ddr region)

Thanks again.