Can FPGA generate pseudo-random codes with a symbol rate of 150Gcps?

Hi, I am currently planning to develop a radar ranging sensor using FPGA, which uses spread spectrum technology. The RF unit of the sensor operates at 7.125GHz, and the spread spectrum code uses M-sequence pseudo-random sequence code. The spread spectrum code is generated by the desired FPGA, with a symbol rate of 150Gcps. Can this design scheme be implemented using FPGA? Or can we implement it using SOC FPGA? As shown in the figure below, cos ωt As an RF carrier, the carrier frequency operates at 7.125GHz, and m1 (t) is used as an m-sequence pseudo-random code. I want to use FPGA to generate it, with a code width of 6.7 picoseconds and a code rate of 150Gcps. The two signals are spread out through a multiplier and then transmitted from the antenna horn. From the current perspective, the clock freq required for 150Gcps is very high. I'm not sure if the clock of Stratix-10, Cyclone-10 or RF SOC FPGA integration solution can meet the requirements?