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Try as I might, I just can't find anywhere in the cyclone5 documents that tells me what is the fastest clock and data rates the cyclone5 GPIO receiver pairs can support to reliably read LVDS data like this. I found some information like that for the special high-speed transceivers in the GX and GT variants, but not the GPIO in any parts. This information is probably right there in front of my face (in those several thousand pages), but I don't see it. What's the answer, and where did you find this information?
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http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf See Table 28 beginning on page 31
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As a separate question, most differential signals I've read about before are "self-timing" (the clock is recovered from the data). But at least some of these image sensors output a LVDS or sub-LVDS clock for every 4 LVDS data signals. Is this supported by the FPGA, or does it expect to recover the clock from the data-signals --- which would make the FPGA operate in a way not consistent with what the image sensors expect?
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You will be writing your own modules (possibly using existing IP or megafunctions as building blocks) to receive your camera data. i.e. the fact that there is a clock and four bits coming at you is something you will be expressing in your Verilog/VHDL. Clock Data Recovery is not something the FPGA demands - you're just wiggling GPIO's.
Probably not exactly useful for your application, but you may want to skim
http://www.altera.com/literature/ug/ug_altlvds.pdf and
http://www.altera.com/literature/ug/ug_altddio.pdf --- Quote Start ---
The device will be sending image data across 4 x 10Ge (10 gigabit ethernet) interfaces. My current idea is to interface to a quad 10GBASE-T PHY via the 32-bit XGMII interfaces. This should make the speed of those (probably non-differential) signals 10Gbps / 32 == 312.5 Mbps (presumably not DDR, but I don't have the specs on the 88x3140 or 88x3240 parts yet). So that's my next question, can the cyclone5 GPIO pins read and write at 320+ Mbps? This is another bit of information about the GPIO speeds that I cannot find (probably very close to the where the speed of LVDS signals is given). What's the answer, and where did you find this information?
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I believe XGMII SDR uses 72-bits @ 156MHz
The capabilities of the devices are in the IO timing spreadsheet:
http://www.altera.com/literature/hb/cyclone-v/cyclonev_io_timing_13.1.xls --- Quote Start ---
I'm guessing the cyclone5 GT parts do not transmit and receive 10GBASE-T signals
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I don't have an answer for your question of tradeoffs, but for what it's worth, I don't think any FPGA terminates twisted pair copper onchip regardless of data rate. Consider not using BASE-T ?
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I fiddled with a cyclone3 FPGA a few years ago, and was amazed they didn't make the FPGA know how to configure itself from standard 1-bit flash memory chips. Instead, you need to buy some fancy and expensive altera configuration chip, or design in an external microcontroller to fiddle pins on the flash memory chip and FPGA chip to configure the FPGA. Has this silliness been eliminated yet, or is this still the situation?
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I believe what you're looking for is "Active Serial" configuration, although there are other options.
Cyclone III is on page 9-13 of
http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf Cyclone V is on page 7-12 of
http://www.altera.com/literature/hb/cyclone-v/cv_52007.pdf
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