Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

can be LVTTL input while LVDS output using PLL?

The input clock of PLL is LVTTL and PLL LVDS output in enhanced mode as pic posted above.

http://photos.i.cn.yahoo.com/04400327037/2bdc/9e75.jpg/ (http://photos.i.cn.yahoo.com/04400327037/2bdc/9e75.jpg/)

I configure the bank of PLL output as LVDS and set OCT in diffierents mode. Can be work and how to chose the minimus drive strength?

BTW: the FPGA chip is Stratix II family and quaturs ACCEPT by the design specification

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hello,

    Also this file isn't accessible to me. Generally, LVDS outputs have a fixed drive strength and no optional terminations, when using LVDS capable outputs, I think. (You don't tell the used FPGA family).

    There has been an issue when using single ended clock input with differential outputs of a PLL, it has been discussed of few months ago. Quartus place&route didn't accept it. This is a bug to my opinion, but I don't know if changes to Quartus have been applied and if all FPGA families are affected. In one case, explicite instantiation of a clock control block could help.

    I believe, that the answer to your question is yes, by specification. If you don't find a way to make Quartus accept this combination, ask Altera support how to.

    Regards,

    Frank