Forum Discussion

Honored Contributor

18 years ago

can be LVTTL input while LVDS output using PLL?

The input clock of PLL is LVTTL and PLL LVDS output in enhanced mode as pic posted above. http://photos.i.cn.yahoo.com/04400327037/2bdc/9e75.jpg/ (http://photos.i.cn.yahoo.com/04400327037/2bdc/9e7...

Altera_Forum

Honored Contributor

18 years ago

Thanks FvM.

The FPGA chip family is stratix II and the quartus DO accept the specification.

The pic URL posted as:

http://photos.i.cn.yahoo.com/04400327037/2bdc/9e75.jpg/ (http://photos.i.cn.yahoo.com/04400327037/2bdc/9e75.jpg/)

Forum Discussion

can be LVTTL input while LVDS output using PLL?

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