Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan ALTDDIO_In use LVDS inputs in Cyclone III
I would like to interface a TI ADC08D1520 to a Cyclone III.
It has dual data rate, diff pair outputs, that are electrically compatible with LVDS. At max speed, the data clock (also an LVDS compatible diff pair) runs at 375MHz, and is supposed to clock the data on both edges. Ie the data rate is 750MHz. Should I use the ALTDDIO megafunction to input this data, or, would the following sample VHDL be sufficient: signal data_first, data_second : std_logic_vector(7 downto 0); signal data_combined : std_logic_vector(15 downto 0); first_data: process(CLK, sys_reset) begin if(sys_reset = '1') then data_combined = 0x"0000"; data_first = 0x"00"; elsif(rising_edge(CLK)) then data_combined = data_second & data_first; data_first = data_in; end if; end process; second_data: process(CLK, sys_reset) begin if(sys_reset = '1') then data_second = 0x"00"; elsif(falling_edge(CLK)) then data_second = data_in; end if; end process; Does anyone have direct experience with trying to get a Cyclone III to run this fast? Will I need a Stratix series part instead? David Lecomte3 Replies
Altera_Forum--- Quote Start --- Should I use the ALTDDIO megafunction to input this data, or, would the following sample VHDL be sufficient: --- Quote End --- Try to use the IP cores where you can, at least to start with. You should be able to use either the ALTDDIO or ALTLVDS_RX components. I suspect if you configure the ALTLVDS_RX component for demux-by-4 or demux-by-8, it will use DDR registers in the I/O cells, and then implement the deserializer in the fabric. Cheers, Dave- Altera_Forum--- Quote Start --- I suspect if you configure the ALTLVDS_RX component for demux-by-4 or demux-by-8, it will use DDR registers in the I/O cells, and then implement the deserializer in the fabric. --- Quote End --- Yes and no. The software LVDS_RX of Cyclone family FPGAs is implemented through altddio_in blocks, but in contrast to DDR output Cyclone III has no dedicated DDR input registers. --- Quote Start --- The DDR input registers are implemented with three internal logic element (LE) registers for every DQ pin. These LE registers are located in the logic array block (LAB ) adjacent to the DDR input pin. --- Quote End --- In so far, a behavioral DDR input description could potentially achieve the same performance as alltddio_in for Cyclone III. I prefer altddio_in for a clear description of the intended functionality. 375 MHz clock is near specified maximum 437 MHz clock speed of fastest C6 speed class. The remaining sampling window will be respectively small.
- Altera_Forum
As an additional remark, the advantage of using altddio_in is to get automatic location constraints for the registers, as the fitter messages reveal:
--- Quote Start --- Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing --- Quote End ---
