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I suspect if you configure the ALTLVDS_RX component for demux-by-4 or demux-by-8, it will use DDR registers in the I/O cells, and then implement the deserializer in the fabric.
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Yes and no. The software LVDS_RX of Cyclone family FPGAs is implemented through altddio_in blocks, but in contrast to DDR output Cyclone III has no dedicated DDR input registers.
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The DDR input registers are implemented with three internal logic element (LE) registers for every DQ pin. These LE registers are located in the logic array block (LAB ) adjacent to the DDR input pin.
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In so far, a behavioral DDR input description could potentially achieve the same performance as alltddio_in for Cyclone III. I prefer altddio_in for a clear description of the intended functionality.
375 MHz clock is near specified maximum 437 MHz clock speed of fastest C6 speed class. The remaining sampling window will be respectively small.
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