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antonto's avatar
antonto
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Call module output - SystemVerilog

Hello, I have a question and would be glad if somebody could help me, im a bit new to Systemverilog so bear with me! I have a project where i use two boards. First one is Intel DE10- lite and ...
Board Debug
Configuration
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Meaning that you just need to create a top module and port map to low level module and signal as per said


antonto's avatar
antonto
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello, thank you for your time.

How do i do that?