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antonto's avatar
antonto
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Call module output - SystemVerilog

Hello, I have a question and would be glad if somebody could help me, im a bit new to Systemverilog so bear with me! I have a project where i use two boards. First one is Intel DE10- lite and ...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I'm assuming boardTest2.sv is the top-level of your design. It's just a matter of instantiation and making the correct connections. Where is loraPacketGenerator in your design hierarchy? You show instantiations in img2. Is the assumption these are in boardTest2? If so, symType is already there as loraPacketGenerator_0_symval. If you are saying it's lower down in the hierarchy, you just have to create an instantiation at the top that connects to the lower level module and signals.

  • antonto's avatar
    antonto
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello, thank you for your time.

    Im sorry but i didnt quite understand...This is my design hierarchy.