Calibration success but data is not right

using UniPHY DDR3 controller generated by Qsys 12.0.

The board is Stratix IV FPGA development board, 530 edition.

PLL reference clock is 125MHz and DDR working frequence is 300MHz.

Any one has met such problem before?

In my opinion, calibration success means PHY has complished data read and write from DDR3.

I have catched the data on AFI interface, which is all right, so I can only doubt the data path from PHY to DDR.

Any suggestions are welcome!