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Honored Contributor
Honored ContributorCalibration success but data is not right
using UniPHY DDR3 controller generated by Qsys 12.0.
The board is Stratix IV FPGA development board, 530 edition. PLL reference clock is 125MHz and DDR working frequence is 300MHz. Any one has met such problem before? In my opinion, calibration success means PHY has complished data read and write from DDR3. I have catched the data on AFI interface, which is all right, so I can only doubt the data path from PHY to DDR. Any suggestions are welcome!1 Reply
Altera_ForumNot sure if you're beyond this point now but if you're still stuck, I'd recommend taking a look at the EMIF toolkit. You'll have to get Qsys up and running but the toolkit gives some good info about the interface. I had good success with it for my DDR2 devices. See Volume 3, Chapter 11 in the EMIF Handbook.
http://www.altera.com/literature/lit-external-memory-interface.jsp
