Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Calibration success but data is not right

using UniPHY DDR3 controller generated by Qsys 12.0. The board is Stratix IV FPGA development board, 530 edition. PLL reference clock is 125MHz and DDR working frequence is 300MHz. An...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Not sure if you're beyond this point now but if you're still stuck, I'd recommend taking a look at the EMIF toolkit. You'll have to get Qsys up and running but the toolkit gives some good info about the interface. I had good success with it for my DDR2 devices. See Volume 3, Chapter 11 in the EMIF Handbook.

http://www.altera.com/literature/lit-external-memory-interface.jsp