calculator arcsin(x)

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but how command in vhdl support convert real to integer and it can synthesised?

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to cast from real to integer:

signal r : real;

siganl i : integer;

begin

i <= integer(r);

But no, it cannot be synthesized. real types CANNOT be synthesised at all. forget about real types. specify a fixed point type you can use instead. Look at this package:

http://www.vhdl.org/fphdl/vhdl.html

It does support floating point (arrays of bits, not real type) but I wouldnt try and synthesis floating point. You'll have a very slow clock.