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Altera_Forum
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14 years ago

cache memory for reading and writing

Hi all I am using a memory of 16 8-bit words that is preloaded with specific operands. My memory module has 5 ports which are "dcenbl" to enable the cache for read or write operation, "rdwr" to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

An initial statement is not synthesizable... it should be used in simulation only.

Either you can instatiate Altera's RAM block or use a reset statement in your always block in which you can initialize the values.