Cache & Addressing

Yes I have the Phycore 5200 B I/O Board which has a MPC 5200 and a Cyclon 2 Fpga device on it and the problem is ;

When I have a UART implemented on the FPGA and want to write something to the UArt's tx register with the command fopr example

*(uint8*)(0xe2000010)=0xa5; // FPGA's UART's tx register is @ 0xe2000010 address from the MPC5200's side;

if the MPC5200's cache is enabled by enabledandicache() function before I send data,the program goes to an exception register,if I disable the cache before I send data by disabledandicache(), there's no problem.

What's the relationship between enabling cache and addressing in MPC5200's side?

Thanx in advance