C4gx dev kit and TSE

Hi,

Perhaps the problem is that the TSE constraints created by QSys are incorrect by default.

If you look into the file YOUR_SYS\synthesis\submodules\YOUR_SYS_tse_mac_constraints.sdc (where YOUR_SYS is the name of your QSys system) you'll see a section "# Customer modifiable constraints" in the beginning of the file, where you're supposed to fill your board's clock names and values.

And if I remember correctly, even the Altera's own examples don't use those pin names and you must change the TSE constraint file before the Ethernet becomes more reliable.

The main problem is that the QSys generates the constraint file every time you generate the QSys system and thus overwrites any changes you've made into that constraint file! Not very user-friendly ...

I've created the following TCL-script (I've named it fix_qsys.tcl) to modify the contraints to match my system's pin names:

 
package require fileutil
proc processContentsOfTseMac {fileContents} {
 #  map search replace
   return 
}
 #  Fix TSE MAC constraints
fileutil::updateInPlace nios_sys/synthesis/submodules/nios_sys_tse_mac_constraints.sdc processContentsOfTseMac

If you add the following line into your project's .qsf file, the Quartus will run the script every time it compiles and thus fix the QSys generated constrains:

 
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:fix_qsys.tcl"

Hope this helps,

Jari