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dnortm's avatar
dnortm
Icon for New Contributor rankNew Contributor
7 years ago

C10GX: Two rx channels on one bank

Hello, I'm trying to implement two high-speed LVDS channels with SERDES logic on the U484 package (Cyclone 10 GX) together with 1866 MHz DDR3L. The problem is that the package has only three banks f...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Dominik,

Kindly find the below info and I request to you to follow the guidelines which is suggested from Intel.

The IOPLL restriction is different for transmitter and receiver.

For transmitter :

TX channels can span three adjacent banks, driven by the IOPLL in the middle bank.

For receiver:

Have to use IOPLL from same bank,

Kindly find the reference for the above in page no: 38 from the below document.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

Regards,

Rahul S