New Contributor
New ContributorHi,
Basically, In Xilinx I have three counters having same source code whose output that is X[9] count (last count) goes to one of the inputs of NOR Gate through bus tap and further to CLK of counter and counter works respectively for next reset signal as shown in Xilinx_V1 image attached. Also, the same count X[9] of counter goes to further combinational logic.
So, while I replicate this same in Quartus, I cannot use three counters with same source code as quartus gives error for Q1[9], if I use it for all three counters. So, for this currently I have used three counters having output Q1[9], Q2[9], Q3[9] with three different source codes namely counter1, counter2, counter3. I have attached image named Intel for reference.
My question is: 1. Will Q1[9] interpret 9th count of counter1 and feed it back to one of the input of NOR Gate correctly?
2. Is there any way where I can use counter with same source code for three times as used in Xilinx ?
Please suggest the possible solution to this.
Super ContributorWhat is the error message that Quartus is showing?
I’m not quite sure why Counter 1, 2, and 3 have different source codes. Aren’t they supposed to have the same functionality, just with different entity names? By the way, the picture is a bit blurry, so it’s hard to make out the details. Perhaps you could run the project using HDL code instead of schematic design.
Alternatively, with the verilog file e.g. counter.v verilog file, you can right-click the file for drop down option, click Create Symbol Files from Current Files to generate the symbol files. Now you can insert the counter block in your schematic. However, we still recommend users to use HDL instead using schematic.
Also, does Xilinx provide a way to generate Verilog code from a schematic? If so, perhaps you could try running that code in Quartus?
Please note that we are specializes in the Quartus tool and we are unable to assist with any inquiries or issues related to Vivado.
Regards,
Richard Tan
