Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIf you go down to 150MHz, then a lot more is possible. I'm guessing you can do it with PLL outputs and it should work. But you do need to monitor the timing on the place-and-route, as it can change compile to compile.
When you say altlvds at 1500Mps isn't possible, how come? Note that altlvds has a PLL in it, so you could, for example, drive it with a 150MHz clock, then internally that would crank it up 8x to a 1200Mbps sampling clock, and then deserialize it /8 back to 8-bits of data coming out at 150MHz. Since it's dedicated silicon, it would all be laid out properly and not change compile to compile.