Honored ContributorHello everyone, i am doing image processing on fgpa.
Actually i want to browse the ram content for every row of the image, and whenever the content of the adress is not updated i need to register this adress. I placed the read statement in a for loop but if for example i have 5 adresses that their contents are not updated the output register only the last one. Is there a possible way to register the multiple adresses.
Honored Contributorthis is a little vague? is this is a software or HDL problem? why not post a code example?
Honored ContributorActually i'm doing this project using VHDL as a description language. Here's my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.math_real.all;
library std;
entity active_tag is
generic
(
DATA_WIDTH : natural
);
port
(
clk : in std_logic;
addr_a : in std_logic_vector(2 downto 0);
addr_b : in std_logic_vector(2 downto 0);
data_a : in integer;
we_a,rd_en : in std_logic := '1';
we_b : in std_logic := '1';
q : out integer;
q_a : out std_logic_vector(DatA_WIDTH-1 downto 0);
q_b : out std_logic_vector(Data_WIDTH-1 downto 0)
);
end active_tag;
architecture rtl of active_tag is
signal data1: std_logic_vector((DATA_WIDTH-1) downto 0);
signal add_a,add_b : integer range 0 to 7;
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(7 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
begin
add_a<=to_integer(unsigned(addr_a));
data1<=std_logic_vector(to_unsigned(data_a,data1'length));
-- Port A
process(clk)
variable i : integer:=1 ;
begin
if(rising_edge(clk)) then
if(we_a = '1') then
ram(add_a) := data1;
end if;
if rd_en='1' then
for add_a in 0 to 7 loop
if (ram(add_a)=(y-1 mod 3)) then
q_a<=std_logic_vector(to_unsigned(add_a,q_a'length));
end if;
end loop;
end if;
end if;
end process;
-- Port B
process(clk)
begin
if(rising_edge(clk)) then
if(we_b = '1') then
ram(add_b) := "000";
q_b <= addr_b;
end if;
end if;
end process;
end rtl;
This code will not work in an FPGA. You can only access a single ram element per clock cycle. So this design will be implemented in logic.
Using a loop the way you have is NOT good practice. For example, here, if two addresses are a match, then it is the last one that will output to q_a. Do you know what circuit you expect from this code? have you got a diagram of it?Honored ContributorYes i know this circuit is implemented in logic but i thought this the only way i can check the ram content. Is there a possible way to browse ram content and get multiple adresses as output without using a for loop? knowing that it's not necessary to get all this adresses in just one clock cycle.
Honored ContributorHonored ContributorThe adresses are not incremented like this, actually they are ouputs from another block so it's like that they are random adresses. I can't tell when they are generated neither their value.
Honored ContributorIt sounds like you are trying to make CAM - content addressable ram. This is not easy in an FPGA.
Also, your code looks like software rather than hardware. for loops in HDL are unrolled to make parallel or sequential logic. In your case, it is create 8 comparators and a 8-1 mux to select the correct ram register (because it is not a ram, its a load of registers) to use. because you are muxing 8-1, comparing then muxing the result again in a single clock cycle, your Fmax is going to be very slow.Honored ContributorThank you so much for your help. I will try to read about the CAM and hope for understanding it, because for the code i published i used 8 elements just for simplification but in my project i have 640 elements.
Honored ContributorHonored ContributorActually i found a vhdl code in this forum about cam on cyclone iii (as i need) it is emulated and uses ram blocks. But the number of the output pins are greater then the available ones. I think about using virtual pins but can this affect my code when i will implement it on my fpga?
