bpsk demodulator with phase lock

BPSK costas loop is a subset of Costas loop for qpsk/16qam etc.

You can design an NCO inside fpga with its accumulator incremented/decremented according to phase error(with appropriate scaling) and in the correct sense.

The loop consists of two branches(sin/cos multiplied by same input). This multiplication produces a sideband that need to be filtered.

The phase error is then the result of product of the the two filtered branches.

The error itself needs its own filter to smooth it out and control the loop(normally an IIR filter with its cutoof controlled by alpha factor).

Once the design is done it will require plenty of effort to tune the loop i.e. find out alpha that gives best loop jitter.

So it is plenty of work.

Moreover, in a practical receiver the clock may also need its own recovery loop.

The front end of receivers requiring clock recovery and phase tracking is a formidable job but not so on block diagrams at Uni