BPSK Demodulation

I solved it Kazem!

Here is the code:

load LPF.mat
N = length(rf_signal);
cos_out = zeros(1, N);
sin_out = zeros(1, N);
phi_inc = zeros(1, N);
bb_sig_I = zeros(1, N);
bb_sig_Q = zeros(1, N);
I_f = zeros(1, N);
Q_f = zeros(1, N);
error_sig = zeros(1, N);
alpha = 0.1;
t = 1:N;
fs = 1.0E8;
fc = 5.0E6;
for i = 1:N
    cos_out(i) = cos(2*pi*fc*t(i)/fs + phi_inc(i));
    sin_out(i) = sin(2*pi*fc*t(i)/fs + phi_inc(i));
    % Downconverting to Baseband
    bb_sig_I(i) = rf_signal(i)*cos_out(i);
    bb_sig_Q(i) = rf_signal(i)*sin_out(i);
    % Filtering
    tmp = filter(LPF, filter(LPF, bb_sig_I(1:i)));
    I_f(i) = tmp(i);
    tmp = filter(LPF, filter(LPF, bb_sig_Q(1:i)));
    Q_f(i) = tmp(i);
    
    % Error
    error_sig(i) = (5*10^-5)*pi*sign(I_f(i)*Q_f(i));
    phi_inc(i+1) = phi_inc(i) - error_sig(i);
end

I replaced my NCO with a cos & sin functions to speed up the execution.

Filtering is done as you suggested.

Error signal is calculated in a slightly different way I found online, but this doesn't require IIR or Loop Filter.

https://www.alteraforum.com/forum/attachment.php?attachmentid=10382

https://www.alteraforum.com/forum/attachment.php?attachmentid=10383

Well, I think this is the desired result... but I don't understand error signal calculation.

Can you please explain it a little bit and how different is it from the previous one?

And I believe this is only theoretical, and can't be implemented in FPGA. Right? How should I modify it to simulate hardware?