Boundary-scan testing with Arria GX and Stratix III

Your question does not make any sense.

Boundary Scan testing of the FPGA and surrounding parts will be executed via the JTAG connection to the part.

The pins that you have listed may or may not be used to configure the FPGA.

They are non related items.

Please re-read the topics on configuration of the FPGA to better understand the function of loading (configurating) the part.

Then after configuration, if you wish to use the JTAG interface for Boundary Scan, just use the JTAG pins.

I hope this makes sense.