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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

bootselect pins confusion

Hello, I am a bit confused with bootselect pins on arria V. According to table A-1 from Arria V Device Handbook: 0x0 Reserved 0x1 FPGA (HPS-to-FPGA bridge) 0x2 1.8 V NAND flash memory 0x3 3.0 ...
rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thanks,

But I find it a bit strange, if they are boot selects pins, it means that they are connected to '0' or '1', not to other device.

So, how can such pin have both roles ?

Thanks

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I do not really get the question, correct me if I am wrong are you asking why there are two boot select pins for NAND devices?