Block vs Distributed RAM

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The "Distributed" Ram is a Xilinx terminology, The Altera terminology doesn't call it this, but it can do something similar, in that they can use the registers in the LE's as ram cells. But this eats (In both Xilinx and Altera fabrics)

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Xilinx's distributed RAM feature uses each LE as a 16x1 or 32x1 bit RAM.

With Altera, you only get 1 bit per LE.

Pyushim,

a) Altera FPGAs don't have a "distributed RAM" feaure like Xilinx do.

b) no

c) FPGA configuration is stored on dedicated RAM cells, which are not available for use as part of the design.